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1 features ? advanced, high-speed programmable logic device ? superset of 22v10 ? improved performance - 7.5 ns t pd , 95 mhz external operation ? enhanced logic flexibility ? backward compatible with atv750(l) software and hardware ? new flip-flop features ? d- or t-type ? product term or direct input pin clocking ? high-speed erasable programmable logic devices ? 7.5 ns maximum pin-to-pin delay ? highest density programmable logic available in a 24-pin package ? increased logic flexibility ? 42 array inputs, 20 sum terms and 20 flip-flops ? enhanced output logic flexibility ? all 20 flip-flops feed back internally ? 10 flip-flops are also available as outputs ? full military, commercial and industrial temperature ranges logic diagram description the atv750b(l) is twice as powerful as most other 24-pin programmable logic devices. increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. high-speed logic and uniform, predictable delays guarantee fast in-system performance. device i cc , standby atv750b 125 ma atv750bl 15 ma high-speed uv erasable programmable logic device atv750b atv750bl commercial, industrial, and military versions are obsolete. please use atf750c. rev. 0301j?07/07 pin configurations pin name function clk clock in logic inputs i/o bi-directional buffers * no internal connection v cc +5v supply dip/soic 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk/in in in in in in in in in in in gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o in plcc/lcc 5 6 7 8 9 10 11 25 24 23 22 21 20 19 in in in * in in in i/o i/o i/o * i/o i/o i/o 4 3 2 1 28 27 26 12 13 14 15 16 17 18 in in gnd * in i/o i/o in in clk/in * vcc i/o i/o
2 atv750b(l) 0301j?07/07 each of the atv750b(l) 22 logic pins can be us ed as an input. ten of these can be used as inputs, outputs or bi-directional i/o pins. each flip-flop is indivi dually configurable as either d- or t-type. each flip-flop output is fed back into the array independently. this allows burying of all the sum terms and flip-flops. there are 171 total product terms available. a variable format is used to assign between four to eight product terms per sum term. there are two sum terms per output, providing added flexibility. much more logic can be replaced by this device th an by any other 24-pin pld. with 20 sum terms and flip-flops, complex state ma chines are easily implemented with logic to spare. product terms provide individual clocks and asynch ronous resets for each flip-flop. each flip- flop may also be individually configured to have direct input pin controlled clocking. each out- put has its own enable product term. one product term provides a common synchronous preset for all flip-flops. register preload function s are provided to simplify testing. all registers automatically reset upon power-up. the atv750bl is a low-power device with speeds as fast as 15 ns. the atv750bl provides the optimum low-power pld solution, with full cmos output levels. this device significantly reduces total system power, thereby allowing battery-powered operation. logic options absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc which may under- shoot to -2.0v for pulses of less than 20 ns.maximum output pin voltage is v cc + 0.75v dc which may overshoot to +7.0v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) integrated uv erase dose..............................7258 w ? sec/cm 2 combinatorial output combined terms separate terms registered output combined terms separate terms
3 atv750b(l) 0301j?07/07 clock mux output options note: 1. see ordering information for valid speed and temperature combination. select logi c to cell clock product term clk cki ckmux pin dc and ac operating conditions (1) commercial -7, -10, -15 commercial -25 industrial military operating temperature 0c - 70c (ambient) 0c - 70c (ambient) -40c - 85c (ambient) -55c - 125c (case) v cc power supply 5v 5% 5v 10% 5v 10% 5v 10%
4 atv750b(l) 0301j?07/07 note: 1. not more than one output at a time should be shorte d. duration of short circuit test should not exceed 30 sec. dc characteristics symbol parameter condition min typ max units i li input load current v in = -0.1v to v cc + 1v 10 a i lo output leakage current v out = -0.1v to v cc + 0.1v 10 a i cc power supply current, standby v cc = max, v in = max, outputs open b-7, -10 com. 125 180 ma ind., mil. 125 190 ma b-15, -25 com. 125 180 ma ind., mil. 125 190 ma bl-15 com. 15 30 ma ind., mil. 15 30 ma i os (1) output short circuit current v out = 0.5v -120 ma v il input low voltage 4.5 v cc 5.5v -0.6 0.8 v v ih input high voltage 2.0 v cc + 0.75 v v ol output low voltage v in = v ih or v il , v cc = min i ol = 16 ma com., ind. 0.5 v i ol = 12 ma mil. 0.5 v i ol = 24 ma com. 0.8 v v oh output high voltage v in = v ih or v il , v cc = min i oh = -100 a v cc - 0.3 v i oh = -4.0 ma 2.4 v input test waveforms and measurement levels t r , t f < 3 ns (10% to 90%) output test load
5 atv750b(l) 0301j?07/07 ac waveforms, product term clock (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0. 0v and 3.0v, unless otherwise specified. note: 1. see ordering information for valid part numbers. ac characteristics, product term clock (1) symbol parameter -7 -10 b/bl-15 b/bl-25 units min max min max min max min max t pd input or feedback to non-registered output 7.5 10 15 25 ns t ea input to output enable 7.5 10 15 25 ns t er input to output disable 7.5 10 15 25 ns t co clock to output 3 7.5 4 10 5 12 6 20 ns t cf clock to feedback 1 5 4 7.5 5 9 5 10 ns t s input setup time 3 4 8/12 14 ns t sf feedback setup time 3 4 7 7 ns t h hold time 1 2 5/7 5/7 ns t p clock period 7 11 14 17 ns t w clock width 3.5 5.5 7 8.5 ns f max external feedback 1/(t s +t co ) 95 71 50/41 29 mhz internal feedback 1/(t sf +t cf ) 125 86 62 58 mhz no feedback 1/(t p ) 142 90 71 58 mhz t aw asynchronous reset width 5 10 15 20 ns t ar asynchronous reset recovery time 31015 20 ns t ap asynchronous reset to registered output reset 812 1525ns t sp setup time, synchronous preset 4 7 8 15 ns
6 atv750b(l) 0301j?07/07 ac waveforms, input pin clock (1) note: 1. timing measurement reference is 1.5v. input ac driving levels are 0. 0v and 3.0v, unless otherwise specified. ac characteristics, input pin clock symbol parameter -7 -10 b/bl -15 b/bl -25 units min max min max min max min max t pd input or feedback to non-registered output 7.5 10 15 25 ns t ea input to output enable 7.5 10 15 25 ns t er input to output disable 7.5 10 15 25 ns t cos clock to output 0 6.5 0 7 0 10 0 12 ns t cfs clock to feedback 0 3.5 0 5 0 5.5 0 7 ns t ss input setup time 4 6.5 8/12.5 9/15 ns t sfs feedback setup time 4 5 7 9 ns t hs hold time 0 0 0 0 ns t ps clock period 7 10 12 16 ns t ws clock width 3.5 5 6 8 ns f maxs external feedback 1/(t ss +t cos ) 95 74 55/44 48/37 mhz internal feedback 1/(t sfs +t cfs ) 133 100 80 62 mhz no feedback 1/(t ps ) 142 100 83 62 mhz t aw asynchronous reset width 5 10 15 20 ns t ars asynchronous reset recovery time 510 15 25 ns t ap asynchronous reset to registered output reset 810 15 25ns t sps setup time, synchronous preset 5 5/9 11 15 ns
7 atv750b(l) 0301j?07/07 functional logic diagram atv750b, upper half
8 atv750b(l) 0301j?07/07 functional logic diagram atv750b, lower half
9 atv750b(l) 0301j?07/07 preload of registered outputs the atv750b(l) registers are provided with circ uitry to allow loading of each register asyn- chronously with either a high or a low. this feature will si mplify testing since any state can be forced into the registers to control test sequencing. a v ih level on the i/o pin will force the reg- ister high; a v il will force it low, independent of the output polarity. the preload state is entered by placing a 10.25v to 10.75v signal on pin 8 on dips, and lead 10 on smds. when the clock term is pulsed high, the data on the i/o pi ns is placed into the register chosen by the select pin. level forced on registered output pin during preload cycle select pin state register #0 state after cycle register #1 state after cycle v ih low high x v il low low x v ih high x high v il high x low
10 atv750b(l) 0301j?07/07 power-up reset the registers in the atv750b(l) is designed to reset during power-up. at a point delayed slightly from v cc crossing v rst , all registers will be reset to th e low state. the output state will depend on the polarity of the output buffer. this feature is critical for state machine initialization. however, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the following condi- tions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock terms or pin high, and 3. the clock pin, or signals from which clock terms are derived, must remain stable during t pr . parameter description typ max units t pr power-up reset time 600 1000 ns v rst power-up reset voltage 3.8 4.5 v pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 58 pf v in = 0v c out 68 pf v out = 0v
11 atv750b(l) 0301j?07/07 using the atv750b(l) many advanced features the atv750b(l) advanced flexibility packs more usable gates into 24- pins than any other logic device. the atv750b(l) starts with the popular 22v10 architecture, and add several enhanced features: ? selectable d- and t-type registers ? each atv750b flip-flop can be individually configured as either d- or t-type. using the t-type configuration, jk and sr flip-flops are also easily created. these options allow more efficient product term usage. ? selectable asynchronous clocks ? each of the atv750b(l) flip-flops may be clocked by its own clock product term or directly from pin 1 (smd lead 2). this removes the constraint that all registers must use the same clock. buried state machines, counters and registers can all coexist in one device while running on separate clocks. individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. ? a full bank of ten more registers ? the atv750b provides two flip-flops per output logic cell for a total of 20. each register has its own sum term, its own reset term and its own clock term. ? independent i/o pin and feedback paths ? each i/o pin on the atv750b has a dedicated input path. each of the 20 registers has its own feedback terms into the array as well. this feature, combined with individual product terms for each i/o?s output enable, facilitates true bi-dir ectional i/o design. programming software support as with all other atmel plds, several third-party development software products support the atv750b(l). several third-party programmers support the atv750b as well. additionally, the atv750b may be programmed to perform the atv750(l)?s functional subset (no t-type flip- flops or pin clocking) using the atv750(l) jede c file. in this case, the atv750b becomes a direct replacement or speed upgrade for the atv750(l). the atv750(l) programming algo- rithm is different from the atv750b algorithm. choose the appropriate device in your programmer menu to ensure proper programming. please refer to the programmable logic development tools section for a complete pld software and programmer listing. synchronous preset and asynchronous reset one synchronous preset line is provided for all 20 registers in the atv750b. the appropriate input signals to cause the internal clocks to go to a high state must be received during a syn- chronous preset. appropriate setup and hold times must be met, as shown in the switching waveform diagram. an individual asynchronous reset line is provided for each of the 20 flip-flops. both master and slave halves of the flip-flops are reset when th e input signals received force the internal resets high. security fuse usage a single fuse is provided to prevent unauthorized copying of the atv750b fuse patterns. once the security fuse is programmed, all fuses will appear program med during verify. the security fuse should be programmed last, as its effect is immediate.
12 atv750b(l) 0301j?07/07 erasure characteristics the entire memory array of an atv750b is erased after exposure to ultraviolet light at a wave- length of 2537 ?. complete erasure is assured after a minimum of 20 minutes exposure using 12,000 w/cm 2 intensity lamps spaced one inch away from the chip. minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 w ? sec/cm 2 . to prevent unintentional erasure, an opaque label is recommended to cover the clear window on any uv-erasable pld which will be subjected to continuous fluorescent indoor lighting or sunlight. atmel cmos plds the atv750b utilizes an advanced 0.65-micron cmos eprom technology. this technol- ogy?s state-of-art features are the optimum combination for plds: ? cmos technology provides high-speed, low-power, and high noise immunity. ? eprom technology is the most cos-effectiv e method for producing plds ? surpassing bipolar fusible link technology in lo w cost, while providing the necessary reprogrammability. ? eprom reprogrammability, which is 100% te sted before shipmen t, provides inherently better programmability and reliability than one- time fusible plds.
13 atv750b(l) 0301j?07/07
14 atv750b(l) 0301j?07/07
15 atv750b(l) 0301j?07/07 ordering information t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code (1) package operation range 7.5 6.5 95 atv750b-7jc atv750b-7pc 28j 24p3 commercial (0 c to 70 c) 10 7 74 atv750b-10jc atv750b-10pc atv750b-10sc 28j 24p3 24s commercial (0 c to 70 c) atv750b-10ji atv750b-10pi atv750b-10si 28j 24p3 24s industrial (-40 c to 85 c) atv750b-10dm/883 atv750b-10lm/883 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant 15 10 58 atv750b-15jc atv750b-15pc atv750b-15sc 28j 24p3 24s commercial (0 c to 70 c) atv750b-15ji atv750b-15pi atv750b-15si 28j 24p3 24s industrial (-40 c to 85 c) atv750b-15dm/883 atv750b-15lm/883 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant 25 15 41 atv750b-25jc atv750b-25pc atv750b-25sc 28j 24p3 24s commercial (0 c to 70 c) atv750b-25ji atv750b-25pi atv750b-25si 28j 24p3 24s industrial (-40 c to 85 c) 10 7 74 5962-88726 08 la 5962-88726 08 3x 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant 15 9 58 5962-88726 09 la 5962-88726 09 3x 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant notes: 1. all ordering codes are obsolete, please use atf750c versions.
16 atv750b(l) 0301j?07/07 using ?c? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ?i? to the ?c? device (7 ns ?c? = 10 ns ?i?) and de-rate power by 30%. 15 9 92 atv750bl-15jc atv750bl-15pc atv750bl-15sc 28j 24p3 24s commercial (0 c to 70 c) atv750bl-15ji atv750bl-15pi atv750bl-15si 28j 24p3 24s industrial (-40 c to 85 c) atv750bl-15dm/883 atv750bl-15lm/883 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant 25 15 37 atv750bl-25jc atv750bl-25pc atv750bl-25sc 28j 24p3 24s commercial (0 c to 70 c) atv750bl-25ji atv750bl-25pi atv750bl-25si 28j 24p3 24s industrial (-40 c to 85 c) 15 9 92 5962-88726 11 lx 5962-88726 11 3x 24dw3 28lw military/883c (-55 c to 125 c) class b, fully compliant package type 24dw3 24-lead, 0.300" wide, windowed, ceramic dual inline package (cerdip) 28j 28-lead, plastic j-leaded chip carrier otp (plcc) 28lw 28-pad, windowed, ceramic leadless chip carrier (lcc) 24p3 24-lead, 0.300" wide, plastic dual inline package otp (pdip) 24s 24-lead, 0.300" wide, plastic gull wing small outline otp (soic) ordering information (continued) t pd (ns) t cos (ns) ext. f maxs (mhz) ordering code (1) package operation range notes: 1. all ordering codes are obsolete, please use atf750c versions.
17 atv750b(l) 0301j?07/07 packaging information 24d3 ? cerdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 24dw3 , 24-lead, 0.300" wide. windowed, ceramic dual inline package (cerdip) b 24dw3 10/21/03 dimensions in millimeters and (inches). controlling dimension: inches. mil-std 1835 d-9 config a (glass sealed) 32.51(1.280) 31.50(1.240) pin 1 7.87(0.310) 7.24(0.285) 0.127(0.005) min 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 1.65(0.065) 1.14(0.045) 8.13(0.320) 7.37(0.290) 10.20(0.400) max 0.46(0.018) 0.20(0.008) 2.54(0.100)bsc 5.08(0.200) 3.18(0.125) seating plane 5.08(0.200) max 27.94(1.100) ref 0o~ 15o ref
18 atv750b(l) 0301j?07/07 28j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. b 28j , 28-lead, plastic j-leaded chip carrier (plcc) 28j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-018, variation ab. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 12.319 ? 12.573 d1 11.430 ? 11.582 note 2 e 12.319 ? 12.573 e1 11.430 ? 11.582 note 2 d2/e2 9.906 ? 10.922 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
19 atv750b(l) 0301j?07/07 28lw ? lcc 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28lw , 28-pad, windowed, ceramic lid, leadless chip carrier (lcc) b 28lw 10/23/03 dimensions in millimeters and (inches). controlling dimension: inches. mil-std 1835 c-4 11.68(0.460) 11.23(0.442) 11.68(0.460) 11.23(0.442) 2.79(0.110) 2.41(0.095) 1.91(0.075) 1.40(0.055) index corner 0.635(0.025) 0.381(0.015) x 45? 0.305(0.012) 0.178(0.007) radius 0.737(0.029) 0.533(0.021) 1.02(0.040) x 45? pin 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 2.16(0.085) 1.65(0.065) 7.62(0.300) bsc 1.27(0.050) typ 7.62(0.300) bsc
20 atv750b(l) 0301j?07/07 24p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 24p 3 , 24-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) d 24p3 6/1/04 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimen s ion s (unit of measure = mm) s ymbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 31.623 ? 32.131 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.651 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation af. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
21 atv750b(l) 0301j?07/07 24s ? soic 0o ~ 8 o pin 1 id pin 1 06/17/2002 2 3 25 orch a rd p a rkw a y sa n jo s e, ca 951 3 1 title drawing no. rev. 24s , 24-le a d (0. 3 00" body) pl as tic g u ll wing s m a ll o u tline ( s oic) b 24 s r common dimensions (unit of me asu re = mm) symbol min nom max note a ? ? 2.65 a1 0.10 ? 0. 3 0 d 10.00 ? 10.65 d1 7.40 ? 7.60 e 15.20 ? 15.60 b0. 33 ? 0.51 l 0.40 ? 1.27 l1 0.2 3 ?0. 3 2 e 1.27 b s c b d d1 e e a a1 l1 l
22 atv750b(l) 0301j?07/07 revision history revision level ? release date history j ? july 2007 obsoleted military-grade versions of the atv750b/bl.
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